The process of implementing a circuit design within a programmable logic device (PLD) typically begins with an architecture description of the circuit design. This description can be specified in a hardware description language such as Verilog or VHDL. Most circuit designs have one or more timing requirements that must be observed. The timing requirements, also called timing constraints, can be expressed within the programmatic description of the circuit design or as supplemental information or files accompanying the circuit design.
Electronic Design Automation (EDA) tools can process the circuit design in an attempt to find an implementation for a given PLD that meets the timing requirements. The EDA tool typically converts the HDL description of the circuit design into a gate-level representation of the circuit design. With respect to field programmable gate array type PLDs, the gate level description can be technology mapped to vendor specific structures available within the PLD. Elements of the circuit design are assigned to different components of the PLD, e.g., lookup tables, flip-flops, block random access memories, processors, configurable logic blocks, and the like.
The EDA tool can place the technology mapped circuit design. The terms “placing” and “placement’ refer to the assignment of elements of the circuit design, now associated with component types available on the PLD, to pre-fabricated sites, or locations, on the PLD. After placement, connections of the circuit design can be routed to generate a routed circuit design. The resulting circuit design is transformed into a bitstream that, when loaded into the PLD, configures the PLD to implement the circuit design.
Reduction in internal delays of PLDs can increase operational speed and efficiency. In earlier PLDs, logic delays were largely dominant over interconnect delays. That is, delays associated with the components of PLDs were larger than the delays associated with the wires connecting those components. With the growing complexity of modern PLDs and the proliferation of sub-micron technology, interconnect delays have become dominant over logic delays. As such, any attempts to reduce delay in modern PLDs must address interconnect delays to be effective.